Without EUV mask aligner, it doesn't mean that chip companies in China can't realize the 3-nanometer process. Through advanced packaging technology, Chinese chip enterprises can make use of the existing technology level to achieve higher chip performance and lower chip cost, thus narrowing the gap with the international advanced level and even taking the lead in some fields.
To put it simply, a large chip with higher performance and lower power consumption is formed by combining a number of small chips with different functions or different materials through special connection methods. This method can avoid the problems of low yield, high cost and poor heat dissipation faced by a single large chip, and can also realize interoperability and cooperative work among different processes, materials and architectures.
Advanced packaging technology mainly includes the following types:
1, 2.5D packaging
A plurality of chiplets are connected by metal interconnection on a silicon substrate or a glass substrate to form a planar structure. This method can improve signal transmission speed and bandwidth, and reduce power consumption and delay.
2, 3D packaging
A plurality of chiplets are connected by vertical metal interconnection to form a three-dimensional structure. This method can further shorten the signal transmission distance and time and improve the integration and performance.
3. Fan-out package
A plurality of chiplets are wrapped by molding compound, and a rewiring layer (RDL) is formed on their surfaces to realize the connection with an external circuit board. This method can reduce package size and cost, and improve reliability and heat dissipation performance.
4.CowOS (Chip on Chip on Substrate) package.
A plurality of chiplets are connected to a wafer through 2.5D package, and then the whole wafer is connected to a substrate. This method can achieve higher signal bandwidth and lower power consumption, and is suitable for high performance computing and artificial intelligence.