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PSP internal structure problem!
Princeton system (von Neumann)

The structure was searched on Baidu, but it was not dismantled.

PSP CPU is manufactured by 7-layer copper conductor process with 90 nm CMOS technology, and mass-produced by Sony Semiconductor "SCEI Fab" Wafer Factory in Nagasaki Morning Market. It contains 6 million gates and its working frequency ranges from 1 to 333 MHz. The frequency can be adjusted according to the application requirements to achieve the purpose of reducing power consumption.

PSP CPU runs at the system bus frequency of 0.5 ~ 166 MHz (128 bits), so it can be inferred that its frequency doubling is set to 2, and 4 MB embedded DRAM (eDRAM) is integrated. The chip is packaged in 540-pin LFBGA, with a core voltage of 0.8V ~ 1.2V and an I/O voltage of 2.5V~3.3V

PSP CPU is actually a single chip with 90 nm process, which integrates MIPS R4000 32-bit CPU core (1 ~ 333 MHz, including floating-point processor FPU and vector floating-point processor VFPU, with 2.6 gigahertz computing power) and 3D drawing core (rendering engine+surface engine, 512 bit/166 MHz).

Another important part of PSP is media processing unit (MPU), which includes media engine (MIPS R4000 32-bit CPU core, 1 ~ 333 MHz, including floating-point processor FPU), H.264 decoding engine (H.264 hardware acceleration) and virtual action engine (VME), which is a virtual accelerator and can be used dynamically.

Back to the most important 3D drawing core, it is composed of rendering engine and surface engine, and the memory is 2MB EDRAM (512bit/166mhz). The pixel filling rate can reach 664 million per second, and the geometric processing capacity is 35 million polygons per second and 58,000 mosaics (divided into 16).