The Lenovo motherboard diagnostic card displays 81, what should I do?

Insert the card into the PCI card slot of the computer, and then read the numbers from the control table

Motherboard Troubleshooting Card Code Query Manual

Lookup table

A table seen above: (Note)

1, special codes "00" and "FF", and start codes in three cases:

① is always one Other codes of the series, then: "00" or "FF", then the motherboard is OK.

② If the CMOS setting is wrong, no serious failure will affect the continuation of the BIOS self-test, "00" or "FF".

③Set "00" or "FF" or any other startup code as soon as the computer is turned on, and it will not change compared to when the board is not running.

2. Arrange the value cards in ascending order in the table and code the value cards in random order.

3. The undefined code is not listed in the table.

4. The same code represents different meanings for different BIOS (commonly used AMI, Phoenix), so you should determine which type of BIOS your computer belongs to. You may ask your computer to You can also see the startup screen directly from the user manual on the motherboard, or directly from the BIOS chip on the motherboard.

5. For the PCI slot of a few motherboards, the first part of the code is output, but a complete self-test code is output to the ISA slot. It is found that there are very few code outputs for the original ISA slots and complete code outputs for the PCI slots. It is recommended that you try to change the dual-slot card slot after checking the codes without success. Different motherboards have PCI slots, the complete code of the slot is sent. The DELL810 motherboard has only one PCI slot near the CPU. The complete code has been changed to "00" or "FF", while the other slots go to "38" and do not continue. Change.

6. The time required for the reset signal for ISA and PCI is not necessarily synchronized, it is possible for the ISA to start the code, but the PCI reset light has not gone out, so the PCI code stops at the start code. BIOS

Code Award BIOS AMI BIOS Phoenix BIOS and Tandy 3000 00. System configuration for the upcoming control INI19 bootloader. .

01 Processor test 1, processor status verification, if the test fails, the loop is infinite. Testing of processor registers is about to begin and non-maskable interrupts are about to be deactivated. CPU register test is in progress or failed.

02 Determine the type of diagnosis (normal or manufactured). If the keyboard buffer is used, the data contained within it will be invalid. Non-maskable interrupts are disabled by delay. CMOS write/read is in progress or failed.

03 Clear the 8042 keyboard controller's command to issue TESTKBRD (AAH). The power-on delay has been completed. Check for ongoing or malfunctioning parts of the ROM BIOS.

04 8042 keyboard controller reset to verify TESTKBRD. Keyboard controller soft reset/power-on test. Programmable interval timer test is in progress or failed.

05, if repeated manufacturing tests 1-5, existing 8042 control status. Soft reset/power has been determined and ROM is about to be booted. DMA starts such preparations in progress or malfunctions.

The 06 circuit chip makes initial preparations, disables video, parity, DMA circuit slices, and clears DMA circuit slices, all page registers and CMOS shutdown bytes. The boot ROM calculates the ROM BIOS checksum and checks that the keyboard buffer has been cleared. DMA initial page register read/write test is in progress or failed.

07 Processor test to verify the working of CPU registers. ROM BIOS checksum, clear keyboard buffer when keyboard issues BAT (Basic Assurance Test) command. .

08. Initial preparation, CMOS timer, normal update timer cycle.

Having keyboard BAT command, BAT command is about to be written. RAM update check is in progress or failed.

09 EPROM checks the sum and must equal zero to pass. Verify the keyboard's basic assurance test and then verify the keyboard command bytes. The first 64K RAM tests are underway.

0A video interface for initial preparation. Issue the keyboard command byte code and write the command byte data. The first 64K RAM chip or data line failed and shifted. Test 8254 channel 0 at

0B. Write the keyboard controller command byte and issue the block/unlock command to pins 23 and 24. The first 64K RAM odd/even logic failed.

0C test 8254 channel 1. Keyboard controller pins 23, 24 and blocked/unlocked; NOP command issued. The address line of the first 64K RAN is faulty.

0D 1. Check that the CPU speed matches the system clock. 2. Check the control chip programming value to meet the early set. Video channel and honk if failed. The NOP command is processed and then the CMOS shutdown register is tested. The first 64K RAM parity error is 0E testing the CMOS shutdown byte. The CMOS register read/write test is closed and the CMOS checksum will be calculated. The address of the initialized input/output port.

0F tests extended CMOS. CMOS checksum calculated and diagnostic byte written; CMOS initial preparation begins.

10 Test DMA channel 0. CMOS has been initially prepared, and the date and time of the CMOS status register are initially prepared. First 64K RAM failure.

11 Test 1 DMA channel. For initial preparation, the CMOS status register is about to disable the DMA and interrupt controller. First 64DK RAM failure.

12 Test DMA page register. Disable DMA controller, interrupt controllers 1 and 2; upcoming video display and port B for initial preparation. First 64DK RAM failure.

13 Test the 8741 keyboard controller interface. The video display is disabled, port B is in initial preparation; the automatic detection circuit chip/memory is about to be initialized. First 64DK RAM failure.

14 Test the memory update trigger circuit. The initialization of the circuit chip/automatic detection of the memory is completed; the 8254 timer test is about to begin. First 64DK RAM failure.

The 15 tests started with 64K of system memory. Channel 2 timer is half tested; 8254 2 channel timer is nearly finished testing. Five first 64DK RAM failures.

16. Create the 8259 interrupt vector table. The 2nd channel timer test is over; 8254 1st channel timer is about to complete the test. The first 64DK RAM failed.

17-aligned video input/output works if the video BIOS is installed and enabled. The 1-channel timer test has ended; the 8254 0-channel timer is about to complete the test. First 64DK RAM failure.

18 tests video memory and can be bypassed if the optional video BIOS is installed. After the 0 channel timer test ends, the memory update is about to begin. First 64DK RAM failure.

19 test channel 1 interrupt controller (8259) mask bits. A memory update has started and then the memory update has completed. 9. First 64DK RAM failure.

The interrupt controller (8259) mask bit of 1A test channel 2. Triggering the memory update line is to check the ON/OFF time for 15μs. First 64DK RAM failure.

1B tests the CMOS battery power. Full memory update 30 microsecond test; basic 64K memory test coming soon. The first 64DK RAM failed.

1C tests CMOS checksum. 12First 64DK RAM failure.

1D CMOS configuration settings. 13. First 64DK RAM failure.

1E measures the size of system memory and compares it to the CMOS value. 64DK RAM failure.

The 1F test has 64K memory and the largest one is 640K. The first 64DK RAM failed.

20 measures fixed 8259 interrupt bits. Starting basic 64K memory test; testing address lines coming soon. Slave DMA register test is in progress or failed.

21 to maintain a non-maskable interrupt (NMI) bit (parity or input/output channel check). Pass the address line test; to trigger parity. Main DMA register test is in progress or failed.

22 Test the interrupt function of 8259. Triggering the parity end will start the serial data read/write test. The main interrupt mask register test is in progress or failed.

23 Test protected mode virtual 8086 mode and 8086 page method. Basic 64K serial data read/write test OK; any adjustments before interrupt vector initialization are about to begin. The slave interrupt mask register test is in progress or failed.

24 measured extended memory above 1MB. Any adjustments prior to vector initialization are complete, and the initial preparation of the interrupt vector is about to begin. Set the ES segment address register registry to the high end of memory.

All 25 tests except in the first 64K of memory. Completes initial preparation of interrupt vector; spins intermittently to begin reading the 8042's input/output ports. Loading interrupt vector is in progress or failed.

26Exceptions for test protection methods. Reads 8042's input/output port; global data for initial preparation for upcoming spin-up intermittent start. Open the A20 address line; participate in the resolution.

27 Determine the cache control or mask RAM. End of a complete initial preparation of data; interrupt vector for any initial preparation. Keyboard controller test is in progress or failed.

28 determines the cache control or a special 8042 keyboard controller. The preliminary preparation work has been completed to interrupt the way the vector transfers the order color. CMOS power failure/checksum calculation.

29. To modulate colors, color modes are set quickly. Check of CMOS configuration validity is in progress.

2A keyboard controller for initial preparation. Set the color mode, and trigger parity before the upcoming ROM test. Blank 64K memory.

2B disk drive and controller for initial preparation. End of trigger parity; upcoming optional video ROM control checks before any adjustments required. Screen memory test is in progress or failed.

2C checks the serial port and makes initial preparations. Completed previous processing of video ROM control; optional video ROM and control coming soon. Screen initial preparation is in progress or failed.

2D detects the parallel port and makes initial preparations. After completing the optional video ROM control, the upcoming video ROM resumes control after any other processing. The screen retrace test is in progress or failed.

2E hard drive and controller for initial preparation. Recycled video ROM control after processing; EGA/VGA deems it necessary to monitor memory read/write testing. Video ROM detection in progress.

2F detects the math coprocessor and makes initial preparations. No EGA/VGA found; monitor memory read/write test about to begin. .

30 base memory and extended memory. Monitor memory read/write test; scan check coming soon. Works fine on screen.

31 Detect the selected ROM from C800:0 to EFFF:0 and make initial preparations.

Display memory read/write test or scan check failed, another display memory read/write test is coming soon. Monochrome monitors work fine.

The COM/LTP/FDD/sound device I/O chip on the 32 motherboard is programmed to suit the setting values. Pass another monitor memory read/write test; scan another monitor. Color monitor (40) works fine.

33. The video monitor check is over; the relevant types of adjustment switches and actual graphics card testing will begin. The color monitor (80) works fine.

34. Check the display adapter and then set up the display. The timer tick signal interrupts the test in progress or fails.

35. Complete the settings to show the BIOS ROM data area to be checked. A shutdown test is in progress or has failed.

36. Check the BIOS ROM data area; power-on cursor set information. The gate circuit is faulty in A-20.

37. Completed; adjust cursor movement to identify power information to display information about power. Unexpected interrupt in protected mode.

38. Upcoming new cursor position readout for complete power information. RAM test in progress or address failure > FFFFH.

39. The saved cursor position has been read out and the reference information string is displayed. .

3A. The display of the reference message string ends with the display of the upcoming discovery message. Interval timer channel 2 tested or failed.

The 3B OPTI chip (only 486) enables initial preparation of the auxiliary cache. Some display discovery information and the virtual memory test is about to start. The daily calendar clock test is in progress or out of order.

3C creates a flag to allow access to CMOS settings. The serial port test is in progress or failed.

3D initializes keyboard/PS2 mouse/PNP device and total memory nodes. Parallel port test is in progress or failed.

3E attempts to open the L2 cache. The math coprocessor test is in progress or malfunctioning.

40. Preparations have begun for virtual testing of the upcoming video memory. Adjust CPU speed to accurately match external clock.

41 interrupt is turned on, will initialize data to 0:0 to detect memory changes (interrupt controller or bad memory), to recover from the video memory after testing, and prepare the descriptor table. System plug-in board selection failed.

42 displays the window to enter SETUP. The descriptor table is ready for the upcoming virtual memory test mode. Failed to expand CMOS RAM.

43. Sequence in Plug and Play BIO?S, parallel initialization. Enter virtual mode; diagnostic interrupt to be reached. .

44. Implement interrupt (if diagnostic switch is turned on; initial preparation of incoming data to check memory rollover at 0:0.) BIOS interrupt is initialized.

45 Initializes the math coprocessor. Initial preparation of data; about to check memory rollover at 0:0 and find out the size of system memory. .

46. Test memory return, the memory size is calculated, and a page is about to be written to test the memory. Check the ROM version.

47. Upcoming attempts are written to extended memory; approximately 640K memory is written to page of page. .

48. The page has been written to base memory, and the upcoming determined memory exceeds 1MB. Video check, CMOS reconfiguration.

49. Find out 1BM less memory and check; coming up with more than 1MB memory. .

4A. Find more than 1MB of memory and check the BIOS ROM data area. Initialization of video.

4B.

End of check BIOS ROM data area check, upcoming and clear soft reset for over 1MB of memory. .

4C. Clearing more than 1MB of memory (soft reset) Clearing more than 1MB of memory. Block video BIOS ROM. .

4D has cleared more than 1MB of memory (soft reset); the memory size will be saved.

If 4E detects an error, an error message will be displayed on the display and it will wait for the customer to continue pressing. Start the memory test (soft reset) and the upcoming display will show the first 64K memory test. Display copyright information.

4F reads and writes soft and hard data DOS boot. The size of the memory that begins displaying the memory being tested will be updated for both serial and random memory tests.

The current BIOS monitoring CMOS value of the region is 50? stored in CMOS. Completed memory testing under 1MB; sizing and masking of upcoming high-speed memory. CPU type and speed are on the screen.

51. Tested with memory above 1MB. .

52 All ISA read-only memory ROMs are initialized and eventually assigned to the PCI IRQ number for initialization. Completed 1MB+ memory test; upcoming preparation for return to real mode. Enter keyboard detection.

53. If the serial port is not initialized, the parallel port and Plug and Play BIO?s are set to a value. Save the size of CPU registers and memory and will enter real mode. .

54. Successfully opened real mode and the upcoming restore of saved registers is ready to stop. Scan for key

55. The recycled register will deactivate the address line of gate A-20. .

56. Successfully deactivated the A-20 address lines; check the BIOS ROM data area. The keyboard test is over. /gt; 57 The BIOS ROM data area has been checked halfway, continue.

58 The BIOS ROM data area check is completed; the discovery information will be cleared. Set up non-interruptive testing.

59. The information has been cleared and the information shows that the test of DMA and interrupt controller is about to start. .

5A.. Press the "F2" key to set.

5B.. Test the basic memory address.

5C..Testing 640K base memory.

60 hard disk boot sector virus protection functions. Test video memory for DMA page register; upcoming test. Test extended memory.

61 displays the system configuration table. End of year video memory test; upcoming DMA#1 basic register test. .

62 starts to interrupt the system startup of 19H. The test of the DMA#1 basic register will be followed by the test of the DMA#2 register. Test the extended memory address lines.

63. DMA#2 basic register test; to check the BIOS ROM data area.

The 64 BIOS ROM data area has been checked halfway.

65 BIOS ROM data area check completed; DMA device 1 and 2 programming.

The programming of 66 DMA devices 1 and 2 exceeds the preliminary preparation work by using the No. 59 interrupt controller. Optimized configuration of cached registry.

67. 8259 The preliminary preparation work has been completed and the keyboard test is about to begin. .

68. Both external Cache and CPU internal Cache work.

6A.. Test and display external Cache values.

6C ..Show blocked content.

6E..Attached configuration information.

70. Codes for detected errors are sent to the screen for display.

72. There is no error detection.

74. Test the real-time clock.

76. Scanned keyboard errors. Keyboard

7A..Locked.

7C ..Set the hardware interrupt vector.

7E..The math processor test is not installed.

80. The keyboard test is clear, check if any keys are stuck and the keyboard will be restored soon. Turn off programmable input/output devices.

81. Recover keyboard stuck keys after identifying errors, and test commands for the keyboard control port that will soon be released. .

82. The keyboard controller interface test ends by writing the command byte circular buffer for initial preparation. Detect and install the RS232 interface (serial port).

83. The command byte has been written, and the preliminary preparation of global data has been completed; it is necessary to check whether there is a key in the lock. .

84. Check that there are no locked keys and will check for CMOS memory mismatch. Detect and install fixed parallel ports.

85. Checks memory size; exhibits soft errors and password or bypass arrangements. .

86. Check the password for the bypass device before upcoming programming. Reopen programmable I/O devices and detect fixed I/O conflicts.

87. To complete the programming before installation, program the CMOS installation. .

88. Arrange a plan to restore the CMOS clear screen, with upcoming programming behind. Initialize the BIOS data area.

89. Complete arrangement of programs, exhibition power screen information. .

8. The first screen information is displayed. Initialize the extended BIOS data area.

8B. Display: Main and video BIOS are about to be blocked. .

8C. Successfully shielding the main and video BIOS will begin programming any options in the CMOS arrangement. Initialization of the floppy drive controller.

8D. Arrange for optional programming, then check out mouse-swiping and preparatory work. .

8E. Detect mouse and complete initial preparation; upcoming hard disk, floppy disk reset. .

8F. Check the floppy disk for initial preparation of the disk and then use the floppy disk. .

90. Floppy configuration; test for presence of hard disk. The hard disk controller is initialized.

91. The hard disk exists at the end of the test; then configure the hard disk. Initialization of local bus hard disk controller.

92. After the hard disk configuration is completed, check the BIOS ROM data area. Jump to user path 2.

93. BIOS ROM data area half checked; continue.

94 The BIOS ROM data area check is completed, and the basic and extended memory sizes are set. Turn off the address line of A-20.

95. The mouse is responsive and supports hard drive 47 and adjusts the display memory for a nice memory of upcoming checks. Testing shows memory reclamation.

96. Coming up C800: Initial preparation before optional ROM control. "ES segment registry clearing.

97. C800: Initial preparation before optional ROM control is completed, followed by optional ROM inspection and control..

98. Optional ROM control, after any processing of the optional ROM recovery control.

99. Any initial preparation required after the optional ROM test is completed; the data area or base of the timer is to be established. Address of the printer.

9A. Tone returns the operating timer and printer base address; adjusts the RS-232 base address.

9B. After the base address is returned, preliminary preparations for the upcoming coprocessor test are completed.

9C. Initial preparation of the coprocessor is established. manage.

9D. Initial preparation of the coprocessor for the upcoming coprocessor test.

After the initial preparation of the coprocessor is completed, it will check for extended keyboard, keyboard recognition, and numeric lock. Open hardware interrupt.

9F Check extended keyboard, 9E. Set the identification flag, the digital lock is opened or closed, and a keyboard identification command will be issued.

A0 issues a keyboard identification command; the recovery rate is the identification flag of the keyboard. Set time and date. BR /gt; A1. ? Keyboard identification flag restored; cache test..

A2 cache test completed, any soft errors will be displayed soon. Check keypad lock. BR /gt; A3. Finished with soft bugs, the upcoming keyboard hit a set of rates

A4. Adjusted hit rate formula for keyboard, memory wait states. Initialization of keyboard repeat input rate. /gt;A5. Wait for the state's memory to finalize, then clear the screen..

A6 has cleared the screen; about to initiate parity and non-maskable interrupts..

A7. Enable non-maskable interrupt parity control of upcoming optional ROM in E000: any required preliminary work..

A8. Before the end of control ROM E000:0, and then after control, the pre-preparation work of E000 is required: any initial preparation. Clear the "F2" key prompt.

A9 controls E000:0 ROM returns control of upcoming E000: optional ROM after any initial preparation required..

AA. After optional ROM control, initial preparation of E000 ends: 0; configuration of the upcoming display system. Scan the "F2" key to hit.

AC enters settings.

AE.. Clear POST trademark.

B0 ..Check for non-critical errors.

B2.. The power-on self-test is completed and ready to boot into the operating system.

B4 buzzer beeps.

B6..Detect password settings (optional).

B8 ..Clear all instruction sheets.

BC ..Clear the parity value.

BE program default values ??enter the control chip line and modulation binary default value table. Clear the screen (optional).

BF tests CMOS to create value. Detect viruses and prompt for data backup.