When a computer needs to read data from memory, there is usually a "buffer period" before the actual reading, and the length of the "buffer period" is this CL.
Memory delay refers to the corresponding time that the system waits for memory before entering the data access operation ready state, which is usually expressed by four consecutive Arabic numerals, such as "3-4-4-8". When the first number represents the delay required for the memory to read data, it is usually called the CL value.
CL sets lower memory.
It has a high advantage and can be expressed by the total delay time. There is a formula for calculating the total memory delay time, which is = system clock cycle × number of CL modes+access time (tAC).
The concept of access time (tAC), which is the abbreviation of CLK Access Time, refers to the maximum number of input clocks with the maximum CAS delay in nanoseconds, which is completely different from the memory clock cycle, although both of them are in nanoseconds. Access time (tAC) represents the time of reading and writing, and clock frequency represents the speed of memory.
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