Must read when looking up the table:
1. Special codes "00" and "ff" and other start codes appear in three situations:
① Already After a series of other codes appear: "00" or "ff", the motherboard is OK.
② If no errors are set in cmos, minor faults will not affect the continuation of bios self-test, and "00" or "ff" will eventually appear.
③ If "00" or "ff" or other start code appears as soon as the computer is turned on and does not change, the motherboard is not running.
2. This table is sorted by code value from small to large. The order of codes in the card is uncertain.
3. The undefined code is not listed in the table.
4. Different bios (commonly used ami, award, phoenix) have different meanings represented by the same code, so you should find out which type of bios the computer you are testing belongs to. You can check your Computer manual, or view it directly from the bios chip on the motherboard, or directly on the startup screen.
5. On a few motherboards, only part of the code appears in the PCI slot, but the isa slot has a complete self-test code output. And it has been found that there are a few original motherboards where the isa slot has no code output, but the pci slot has a complete code output. Therefore, it is recommended that you change the dual-slot card to another slot and try it if you fail to check the code. . In addition, for different PCI slots on the same motherboard, some slots have complete codes sent out. For example, on the Dell810 motherboard, only one PCI slot close to the CPU has a complete code display, which changes to "00" or "ff", while other PCI slots go to There will be no further changes after "38".
6. The time required for the reset signal is not necessarily synchronized with the PCI, so it is possible that the ISA starts to output the code, but the reset light of the PCI does not go out, so the PCI code stops at the start code.
Code comparison table
00. The system configuration has been displayed; it will control the INI19 boot loader.
01 Processor test 1, processor status verification, if the test fails, the loop is infinite. Testing of processor registers is about to begin and non-maskable interrupts are about to be deactivated. CPU register test is in progress or failed.
02 Determine the type of diagnosis (normal or manufactured). The keyboard buffer will be invalidated if it contains data. Disable non-maskable interrupts; start with delay. CMOS write/read is in progress or failed.
03 Clear the 8042 keyboard controller and issue the TESTKBRD command (AAH). The power-on delay has been completed. The ROM BIOS check component is in progress or malfunctioning.
04 Reset the 8042 keyboard controller and verify TESTKBRD. Keyboard controller soft reset/power-on test. Programmable interval timer test is in progress or failed.
05 If manufacturing tests 1 to 5 are repeated continuously, the 8042 control status can be obtained. Soft reset/power-on confirmed; ROM boot is imminent. DMA is as ready as possible or is out of order.
06 Initial preparation of the circuit chip, disabling the video, parity, DMA circuit chip, and clearing the DMA circuit chip, all page registers and CMOS shutdown bytes. Started ROM calculation of ROM BIOS check sum, as well as checking that the keyboard buffer is cleared. DMA initial page register read/write test is in progress or failed.
07 Processor test 2, verify the working of CPU registers. ROM BIOS checksum is OK, keyboard buffer cleared, issue BAT (Basic Assurance Test) command to keyboard. .
08 Make the CMOS timer make initial preparations and update the timer cycle normally. A BAT command has been issued to the keyboard and the BAT command is about to be written. RAM update check is in progress or failed.
09 EPROM checks the sum and must equal zero to pass.
Verify the basic assurance test of the keyboard, followed by verification of the keyboard command bytes. The first 64K RAM tests are underway.
0A makes initial preparations for the video interface. The keyboard command byte code is issued and the command byte data is about to be written. The first 64K RAM chip or data line failed and shifted.
0B tests 8254 channel 0. Writing the keyboard controller command byte will issue a block/unlock command for pins 23 and 24. The first 64K RAM odd/even logic failed.
0C Test 8254 channel 1. Keyboard controller pins 23, 24 are blocked/unlocked; NOP command issued. The address line of the first 64K RAN is faulty.
0D 1. Check whether the CPU speed matches the system clock. 2. Check whether the programmed value of the control chip matches the initial setting. 3. Video channel test, if it fails, the horn will sound. The NOP command has been processed; then test the CMOS stop-on register. Parity failure of first 64K RAM
0E Test CMOS shutdown byte. CMOS stop open register read/write test; CMOS checksum will be calculated. Initialize the input/output port address.
0F Test extended CMOS. Calculated CMOS checksum written to diagnostic byte; CMOS initial preparation begins. .
10 Test DMA channel 0. CMOS has been initially prepared, and the CMOS status register is about to be initially prepared for date and time. The first 64K RAM bit 0 failed.
11 Test DMA channel 1. The CMOS status register has been initially prepared to disable the DMA and interrupt controller. The first 64DK RAM bit 1 failed.
12 Test DMA page register. Disable DMA controller 1 and interrupt controllers 1 and 2; disable the video display and make port B initially ready. The first 64DK RAM bit 2 failed.
13 Test the 8741 keyboard controller interface. The video display is disabled and port B is initially prepared; chip initialization/memory auto-detection is about to begin. The first 64DK RAM bit 3 failed.
14 Test the memory update trigger circuit. Circuit chip initialization/memory automatic detection ends; 8254 timer test is about to begin. The first 64DK RAM bit 4 failed.
15 Test the first 64K of system memory. Channel 2 timer is halfway tested; 8254 Channel 2 timer is about to complete testing. The first 64DK RAM bit 5 failed.
16 Create the interrupt vector table used by 8259. The 2nd channel timer test is over; the 8254 1st channel timer is about to complete the test. The first 64DK RAM bit 6 failed.
17 Adjust video input/output operation, enable video BIOS if installed. The first channel timer test is over; the 8254 channel 0 timer is about to complete the test. The first 64DK RAM bit 7 failed.
18 Test the video memory. If the installation of the selected video BIOS passes, it can be bypassed. Channel 0 timer test is over; memory update is about to begin. The first 64DK RAM bit 8 failed.
19 Test the interrupt controller (8259) mask bit of channel 1. The memory update has started and will be completed. The first 64DK RAM bit 9 failed.
1A Tests the mask bit of the interrupt controller (8259) of channel 2. Triggering memory update circuit, about to check 15 microsecond on/off time. The first 64DK RAM bit 10 failed.
1B Test CMOS battery level. Completed memory update time 30 microsecond test; basic 64K memory test is about to begin. The first 64DK RAM bit 11 failed.
1C Test CMOS checksum. . The first 64DK RAM bit 12 failed.
1D Set CMOS configuration. . The first 64DK RAM bit 13 failed.
1E Determine the size of system memory and compare it with the CMOS value. . The first 64DK RAM bit 14 failed.
1F tests 64K memory to a maximum of 640K. . The first 64DK RAM bit 15 failed.
20 Measure the fixed 8259 interrupt bit. Begins basic 64K memory test; will test address lines soon. Slave DMA register test is in progress or failed.
21 Maintain the non-maskable interrupt (NMI) bit (parity or input/output channel check). Passes address line test; parity is about to be triggered. Main DMA register test is in progress or failed.
22 Test the interrupt function of 8259. Ends triggering parity; serial data read/write test will begin. The main interrupt mask register test is in progress or failed.
23 Test the protection mode 8086 virtual mode and 8086 page mode. Basic 64K serial data read/write test is OK; any adjustments prior to interrupt vector initialization are about to begin. The slave interrupt mask register test is in progress or failed.
24 Measures extended memory above 1MB. Any adjustments prior to vector initialization are complete, and the initial preparation of the interrupt vector is about to begin. Set the ES segment address register registry to the high end of memory.
25 Test all memories except the first 64K. Complete the initial preparation of the interrupt vector; the input/output port of the 8042 will be read out for the rotating interrupt. Loading interrupt vector is in progress or failed.
26 Test exceptions to protection methods. Read the input/output port of the 8042; it is about to make initial preparations for the rotational interrupt to start the global data. Turn on the A20 address line; enable it to participate in addressing.
27 Determine the cache control or mask RAM. The initial preparation of all 1 data is complete; any initial preparation after the interrupt vector will then proceed. Keyboard controller test is in progress or failed.
28 Identify cache control or special 8042 keyboard controller. Initial preparation after interrupt vector is completed; monochrome mode is about to be set. CMOS power failure/checksum calculation in progress.
29. The monochrome mode has been set and the color mode will be set soon. Check of CMOS configuration validity is in progress.
2A Initializes the keyboard controller. The color mode has been set and the trigger parity before the ROM test is about to be performed. Empty 64K base memory.
2B Initial preparation of disk drives and controllers. Triggers parity end; any adjustments required before controlling the optional video ROM check. Screen memory test is in progress or failed.
2C Checks the serial port and makes initial preparations. Completed before video ROM control; about to view and control optional video ROMs. Screen initial preparation is in progress or failed.
2D detects the parallel port and initially prepares it. Optional video ROM control has been completed and control of any other processing after video ROM recovery control is about to occur. The screen retrace test is in progress or failed.
2E Initial preparation of hard disk drives and controllers. Recover from the processing after video ROM control; if EGA/VGA is not found, perform a display memory read/write test. Detecting video ROM is in progress.
2F Detects the math coprocessor and makes initial preparations for it. No EGA/VGA found; monitor memory read/write test will begin. .
30 Create basic memory and extended memory.
Passed display memory read/write test; scan check coming soon. Think the screen works.
31 Detect the selected ROM from C800:0 to EFFF:0 and make initial preparation. The monitor memory read/write test or scan check failed and another monitor memory read/write test is about to occur. Monochrome monitors work.
32 Program I/O chips such as COM/LTP/FDD/sound equipment on the motherboard to suit the setting values. Passes another monitor memory read/write test; will do another monitor scan check. Color monitors (40 columns) will work.
33. The video monitor inspection is completed; we will start to use the adjustment switch and the actual plug-in card to check the monitor's closing type. Color monitors (80 columns) will work.
34. The display adapter has been verified; the display mode will be adjusted next. The timer tick interrupts a test in progress or failed. 35. The display mode setting is completed; the data area of ??BIOS ROM is about to be checked. A shutdown test is in progress or has failed.
36. The BIOS ROM data area has been checked; the power-on information cursor will be set soon. A-20 failed in the gate circuit.
37. The cursor setting for identifying power-on information has been completed; the power-on information will be displayed soon. Unexpected interruption in protected mode.
38. Completed display of power-on information; new cursor position will be read out. RAM test is in progress or address failure > FFFFH.
39. The saved cursor position has been read out and the reference information string will be displayed. .
3A. The display of the reference information string ends; the discovery information will be displayed soon. Interval timer channel 2 tested or failed.
3B Use the OPTI chip (486 only) to initially prepare the auxiliary cache. The
3C Establishes a flag that allows access to CMOS settings. . Serial port test is in progress or failed.
3D initializes the keyboard/PS2 mouse/PNP device and total memory node. . Parallel port test is in progress or failed.
3E Attempt to open L2 cache. . The math coprocessor test is in progress or failed.
40. Preparations have been started for testing in virtual mode; it will be tested from video storage. Adjust the CPU speed to exactly match the peripheral clock.
41 Interrupt is on, data will be initialized for 0:0 detection of memory transition (interrupt controller or memory bad) Recovering from video memory check; descriptor table is about to be prepared. System plug-in board selection failed.
42 Display window to enter SETUP. Descriptor table is ready; virtual mode memory test is about to begin. Extended CMOS RAM failure.
43 If it is a plug-and-play BIOS, the serial port and parallel port are initialized. Enter virtual mode; interrupt for diagnostic mode is about to be implemented. . 44. Interrupt has been implemented (if the diagnostic switch has been turned on; the data will be initially prepared to check the memory rollover at 0:0.) BIOS interrupt is initialized.
45 Initialize the math coprocessor. The data has been initially prepared; the memory rollover at 0:0 is about to be checked and the size of the system memory is found. .
46. The test memory has been returned; the memory size has been calculated and the page will be written to test the memory. Check the ROM version.
47. A test page will be written in the extended memory; a page will be written in the basic 640K memory.
48. Basic memory has been written to the page; more than 1MB of memory will be determined soon. Video check, CMOS reconfiguration.
49. Find the memory below 1BM and check it; the memory above 1MB will be determined soon. .
4A. Find the memory above 1MB and check it; the BIOS ROM data area will be checked soon. Initialize the video.
4B. The verification of the BIOS ROM data area is completed, and the
4E If an error is detected; display the error message on the monitor and wait for the customer to press the
4F reads and writes soft and hard disk data and performs DOS boot. Starts displaying memory size, Testing Memory will update it; serial and random memory tests will be performed. .
50 Store the CMOS value in the current BIOS monitoring area into CMOS. Complete memory testing below 1MB; that is, the size of high-speed memory for relocation and masking. Send CPU type and speed to the screen.
51. Test memory above 1MB. .
52 All ISA read-only memory ROMs are initialized, and finally allocate IRQ numbers to PCI and other initialization work. The memory test of more than 1MB has been completed; it is about to return to real address mode. Enter keyboard detection.
53 If it is not a plug-and-play BIOS, initialize the serial port, parallel port and setting time values. Save the size of CPU registers and memory and enter real address mode. .
54. The real address mode is successfully turned on; the registers saved when preparing to shut down are about to be restored. Scan the "strike key"
55. The register has been restored and the address line of gate A-20 will be disabled. .
56. Successfully disabled the A-20 address line; about to check the BIOS ROM data area. The keyboard test is over.
57. Half of the BIOS ROM data area has been checked; continue. .
58. The BIOS ROM data area check is completed; the
59. The
5A . . Press the "F2" key to set.
5B . . Test the base memory address.
5C . . Testing 640K base memory.
60 Set the hard disk boot sector virus protection function. Passed test of DMA page register; video memory is about to be verified. Test extended memory.
61 Display the system configuration table. Video memory verification completed; test of DMA#1 basic registers is about to begin. .
62 Start system booting with interrupt 19H. Passed test of DMA#1 basic register; test of DMA#2 register is coming soon. Test the extended memory address lines.
63. Passed the test of DMA#2 basic register; the BIOS ROM data area will be checked soon. .
64. The BIOS ROM data area has been checked halfway, continue. .
65. BIOS ROM data area check completed; DMA devices 1 and 2 will be programmed. .
66. Programming of DMA devices 1 and 2 is completed; interrupt controller No. 59 will be used for initial preparation. Cache registry is optimized and configured.
67. 8259 Initial preparation has ended; keyboard test is about to begin. .
68 . . Make both external Cache and CPU internal Cache work.
6A . . Test and display external Cache values.
6C . . Display blocked content.
6E . . Display accessory configuration information.
70 . . The detected error code is sent to the screen for display.
72. . Check whether there are any errors in the configuration.
74 . . Test the real-time clock.
76 . . Scan for keyboard errors.
7A . . Lock the keyboard.
7C . . Set the hardware interrupt vector.
7E . . Tests whether the math processor is installed.
80. The keyboard test has started, it is clearing and checking whether there are any stuck keys, and the keyboard is about to be restored. Turn off programmable input/output devices.
81. Find out the incorrectly stuck keys for keyboard recovery; a test command for the keyboard control port is about to be issued. .
82. The keyboard controller interface test is completed, and the command bytes will be written and the circular buffer will be initially prepared. Detect and install fixed RS232 interface (serial port).
83. The command byte has been written, and the initial preparation of global data has been completed; it is about to check whether there is a key lock. .
84. Checked whether there is a locked key, and will soon check whether the memory mismatches with CMOS. Detect and install fixed parallel ports. 85. Memory size checked; soft error and password or bypass arrangements will be displayed. .
86. Password checked; programming before bypass arrangement is about to begin. Reopen programmable I/O devices and detect fixed I/O conflicts.
87. Complete the programming before arrangement; the CMOS arrangement will be programmed. .
88. Restore clear screen from CMOS scheduler; subsequent programming is about to begin. Initialize the BIOS data area.
89. Post-arrangement programming completed; power-on screen information will be displayed. .
8A . Display the first screen information. Initialize the extended BIOS data area.
8B. Message displayed: Main and video BIOS will be blocked soon. .
8C . After successfully disabling the main and video BIOS, programming of the CMOS post-arrangement options will begin. Perform floppy drive controller initialization.
8D. Option programming has been arranged, then the mouse is checked and initial preparations are made. .
8E. The mouse has been detected and initial preparations have been completed; the hard and floppy disks are about to be reset. .
8F . The floppy disk has been checked. The disk will be initially prepared and then equipped with a floppy disk. .
90 . Soft disk configuration completed; hard disk presence will be tested. The hard disk controller is initialized.
91. The hard disk existence test is completed; then configure the hard disk. Local bus hard disk controller initialization.
92. The hard disk configuration is completed; the BIOS ROM data area is about to be checked. Jump to user path 2.
93. Half of the BIOS ROM data area has been checked; continue. .
94. The BIOS ROM data area check is completed, that is, the basic and extended memory sizes are set. Close the A-20 address line. 95. Adjust memory size for mouse and hard disk type 47 support; display memory will be tested soon. .
96. Restore after checking the display memory; the initial preparation before C800:0 optional ROM control is about to be carried out. "ES segment" registry clearing.
97. C800: 0 Any initial preparation before optional ROM control is completed, and then the inspection and control of the optional ROM are carried out. . 98 . Control of the option ROM is complete; any processing required after the option ROM returns to control will be performed. Find ROM selections.
99. Any initial preparation required after optional ROM testing is complete; the data area for the timer or the printer base address is about to be established. .
9A. Return operation after setting the timer and printer base address; that is, setting the RS-232 base address. Shield ROM selection.
9B. Return after the RS-232 base address; initial preparation for coprocessor testing is about to begin. .
9C . The initial preparation required before the coprocessor test is completed; then the coprocessor is initially prepared. Establish power supply energy-saving management.
9D. The coprocessor is ready for initial preparation, and any initial preparation after the coprocessor test will be carried out. .
9E . After completing the initial preparation of the coprocessor, the extended keyboard, keyboard identifier, and numeric lock will be checked. Open hardware interrupt.
9F. The extended keyboard has been checked, the identification flag is set, the digital lock is turned on or off, and the keyboard identification command will be issued. .
A0 . Issue a keyboard identification command; the keyboard identification flag will be restored. Set time and date.
A1. The keyboard identification flag is restored; then the cache memory is tested. .
A2 . Cache test completed; any soft errors will be displayed. Check keypad lock.
A3. The soft error display is completed; the keyboard strike speed is about to be set. .
A4 . After adjusting the keyboard's hitting rate, the waiting state of the memory will be established. Initialization of keyboard repeat input rate.
A5. The memory wait state is established; the screen will then be cleared. .
A6 . Screen cleared; parity and non-maskable interrupts are about to be initiated. .
A7 . Non-maskable interrupts and parity are enabled; any initial preparations required to control optional ROM at E000:0 are about to take place. .
A8 . The control ROM ends initial preparation before E000:0 and will then control any initial preparation required after E000:0. Clear the "F2" key prompt.
A9. Returning from controlling the E000:0 ROM, any initial preparation required after controlling the E000:0 optional ROM is about to take place. .
AA . Initial preparation after controlling the optional ROM at E000:0 is complete; the system's configuration is about to be displayed. Scan the "F2" key to hit.
AC . . Enter settings.
AE . . Clear the power-on self-test flag.
B0 . . Check for non-critical errors.
B2 . . The power-on self-test is completed and the system is ready to boot into the operating system.
B4 . . The buzzer sounds once.
B6 . . Detect password settings (optional).
B8 . . Clear all description tables.
BC . . Clear the validation check value.
BE program default values ??enter the control chip and conform to the modifiable binary default value table. . Clear the screen (optional).
BF tests the CMOS establishment value. . Detect viruses and prompt for data backup.
C0 initializes the cache. . Try booting with interrupt 19.
C1 memory self-test. . Look for the "55" "AA" mark in the boot sector.
C3 first 256K memory test. . .
C5 Copy BIOS from ROM for quick self-test.
. .
C6 cache self-test. . .
CA detects the Micronies cache (if present) and makes initial preparations for it. . .
CC shuts down the non-maskable interrupt handler. . .
Unexpected exceptions for EE processors. . .
FF gives control of the INI19 bootloader and the motherboard is OK.
Answer: luckyboy - Great Magician Level 8 6-4 20:34
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